Invention Grant
US08551858B2 Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory
有权
自对准SI丰富的氮化物电荷陷阱层隔离电荷陷阱闪存
- Patent Title: Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory
- Patent Title (中): 自对准SI丰富的氮化物电荷陷阱层隔离电荷陷阱闪存
-
Application No.: US12699635Application Date: 2010-02-03
-
Publication No.: US08551858B2Publication Date: 2013-10-08
- Inventor: Shenqing Fang , Angela Hui , Shao-Yu Ting , Inkuk Kang , Gang Xue
- Applicant: Shenqing Fang , Angela Hui , Shao-Yu Ting , Inkuk Kang , Gang Xue
- Applicant Address: US CA Sunnyvale
- Assignee: Spansion LLC
- Current Assignee: Spansion LLC
- Current Assignee Address: US CA Sunnyvale
- Main IPC: H01L21/76
- IPC: H01L21/76

Abstract:
A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance. U-shaped trap layer edges allow for increased packing density and integration while maintaining isolation between trap layers.
Public/Granted literature
- US20100133646A1 SELF-ALIGNED SI RICH NITRIDE CHARGE TRAP LAYER ISOLATION FOR CHARGE TRAP FLASH MEMORY Public/Granted day:2010-06-03
Information query
IPC分类: