Invention Grant
US08551872B2 Low series resistance transistor structure on silicon on insulator layer 有权
硅绝缘体层上的低串联电阻晶体管结构

Low series resistance transistor structure on silicon on insulator layer
Abstract:
A transistor structure includes a channel located in an extremely thin silicon on insulator (ETSOI) layer and disposed between a raised source and a raised drain, a gate structure having a gate conductor disposed over the channel and between the source and the drain, and a gate spacer layer disposed over the gate conductor. The raised source and the raised drain each have a facet that is upwardly sloping away from the gate structure. A lower portion of the source and a lower portion of the drain are separated from the channel by an extension region containing a dopant species diffused from a dopant-containing glass.
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