Invention Grant
- Patent Title: Method for reducing stress in epitaxial growth
- Patent Title (中): 减少外延生长中的应力的方法
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Application No.: US13293031Application Date: 2011-11-09
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Publication No.: US08552465B2Publication Date: 2013-10-08
- Inventor: Steven D. Lester
- Applicant: Steven D. Lester
- Applicant Address: JP Tokyo
- Assignee: Toshiba Techno Center Inc.
- Current Assignee: Toshiba Techno Center Inc.
- Current Assignee Address: JP Tokyo
- Agency: Hogan Lovells US LLP
- Main IPC: H01L33/12
- IPC: H01L33/12

Abstract:
A device and method for making the same are disclosed. The device includes a substrate having a first TEC, a stress relief layer overlying the substrate, and crystalline cap layer. The crystalline cap layer overlies the stress relief layer. The cap layer has a second TEC different from the first TEC. The stress relief layer includes an amorphous material that relieves stress between the crystalline substrate and the cap layer arising from differences in the first and second TECs at a growth temperature at which layers are grown epitaxially on the cap layer. The device can be used to construct various semiconductor devices including GaN LEDs that are fabricated on silicon or SiC wafers. The stress relief layer is generated by converting a layer of precursor material on the substrate after the cap layer has been grown to a stress-relief layer.
Public/Granted literature
- US20120319160A1 Method for Reducing Stress in Epitaxial Growth Public/Granted day:2012-12-20
Information query
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