Invention Grant
- Patent Title: Segmented pillar layout for a high-voltage vertical transistor
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Application No.: US12455462Application Date: 2009-06-02
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Publication No.: US08552493B2Publication Date: 2013-10-08
- Inventor: Vijay Parthasarathy , Wayne Bryan Grabowski
- Applicant: Vijay Parthasarathy , Wayne Bryan Grabowski
- Applicant Address: US CA San Jose
- Assignee: Power Integrations, Inc.
- Current Assignee: Power Integrations, Inc.
- Current Assignee Address: US CA San Jose
- Agency: The Law Offices of Bradley J. Bereznak
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.
Public/Granted literature
- US20090273023A1 Segmented pillar layout for a high-voltage vertical transistor Public/Granted day:2009-11-05
Information query
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