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US08552509B2 Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors 有权
集成电路包括交叉耦合晶体管，其栅极电极形成在门级特征布局通道内，其它晶体管位于交叉耦合晶体管之间

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors
Abstract:
A semiconductor device includes conductive features that are each defined within any one gate level channel uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along second and third gate electrode tracks, respectively. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.
Abstract(Chinese):

半导体器件包括导电特征，每个导电特征各自被限定在与多个平行栅极电极轨道中的一个栅极电平通道唯一相关联并且沿着多个平行栅极电极轨迹中 导电特征形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一PMOS和第一NMOS晶体管器件的栅电极沿着第一栅电极轨道延伸。 第二PMOS和第二NMOS晶体管器件的栅电极分别沿着第二和第三栅电极迹线延伸。 第一组互连导体电连接第一PMOS和第二NMOS晶体管器件的栅电极。 第二组互连导体电连接第二PMOS和第一NMOS晶体管器件的栅电极。 第一组和第二组互连导体在半导体器件的不同级别内横越彼此。

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