Invention Grant
US08552518B2 3D integrated microelectronic assembly with stress reducing interconnects 有权
具有减压互连的3D集成微电子组件

  • Patent Title: 3D integrated microelectronic assembly with stress reducing interconnects
  • Patent Title (中): 具有减压互连的3D集成微电子组件
  • Application No.: US13157202
    Application Date: 2011-06-09
  • Publication No.: US08552518B2
    Publication Date: 2013-10-08
  • Inventor: Vage Oganesian
  • Applicant: Vage Oganesian
  • Applicant Address: US CA Palo Alto
  • Assignee: Optiz, Inc.
  • Current Assignee: Optiz, Inc.
  • Current Assignee Address: US CA Palo Alto
  • Agency: DLA Piper LLP (US)
  • Main IPC: H01L31/00
  • IPC: H01L31/00
3D integrated microelectronic assembly with stress reducing interconnects
Abstract:
A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handier with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.
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