Invention Grant
- Patent Title: Methods for forming three-dimensional memory devices, and related structures
- Patent Title (中): 形成三维记忆装置的方法及相关结构
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Application No.: US13450960Application Date: 2012-04-19
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Publication No.: US08552568B2Publication Date: 2013-10-08
- Inventor: Nishant Sinha , Krishna K. Parat
- Applicant: Nishant Sinha , Krishna K. Parat
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Traskbritt
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L21/44 ; H01L21/48 ; H01L21/50

Abstract:
Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods.
Public/Granted literature
- US20120199987A1 METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES, AND RELATED STRUCTURES Public/Granted day:2012-08-09
Information query
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