Invention Grant
- Patent Title: Method of measuring delay in an integrated circuit
- Patent Title (中): 测量集成电路延迟的方法
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Application No.: US12747650Application Date: 2008-12-10
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Publication No.: US08552740B2Publication Date: 2013-10-08
- Inventor: Peter Ying Kay Cheung , Nicholas Peter Sedcole , Justin Sung-Jit Wong
- Applicant: Peter Ying Kay Cheung , Nicholas Peter Sedcole , Justin Sung-Jit Wong
- Applicant Address: GB London
- Assignee: Maxeler Technologies Limited
- Current Assignee: Maxeler Technologies Limited
- Current Assignee Address: GB London
- Agency: Hickman Palermo Truong Becker Bingham Wong LLP
- Priority: GB0724177.1 20071211
- International Application: PCT/GB2008/004069 WO 20081210
- International Announcement: WO2009/074790 WO 20090618
- Main IPC: G01R23/12
- IPC: G01R23/12 ; G01R23/175 ; G06F19/00
Abstract:
A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal.
Public/Granted literature
- US20110095768A1 METHOD OF MEASURING DELAY IN AN INTEGRATED CIRCUIT Public/Granted day:2011-04-28
Information query
