A system including a first clock module, a second clock module and an adjustment module. The first clock module is configured to generate a first clock signal having a first frequency. The second clock module is configured to, based on the first clock signal, generate a second clock signal for an integrated circuit. An amount of current drawn by the integrated circuit is based on a second frequency of the second clock signal. An adjustment module is configured to receive an enable signal indicating whether the integrated circuit is being powered ON. In response to the enable signal indicating the integrated circuit is being powered ON, the adjustment module (i) determines a predetermined frequency, and (ii) generate a control signal based on the first clock signal. The control signal adjusts the second frequency of the second clock signal to be between the predetermined frequency and the first frequency.