A CMOS circuit and a semiconductor device having small leakage current and a low threshold voltage, and which is operated at high speed and with a small voltage amplitude, including an output stage circuit having MOSTs configured such that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, and upon deactivation, a voltage is applied to the gate of each of the MOSTs to cause a reverse bias to be applied between the gate and source of the MOST. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage.