Method and circuit topology for an impedance compensation circuit (ICC), for compensating a DC voltage regulator circuit (RC). The ICC comprises individual components that are workable in combination with an inherent output impedance characteristic of the RC. The components are optimizable for providing a substantially uniform AC output impedance characteristic and impedance phase over a first defined frequency range and an operating idle current under a load, by creating a condition where a source impedance and a load impedance are complex conjugates. The source impedance is a series combination of the inherent output impedance characteristic of the RC and a first impedance due to a first portion of the individual components. The load impedance is a parallel combination of a second impedance due to a second portion of the individual components and the load, when the ICC is configured with the RC and the load.