A control circuit controls various kinds of operations on the memory cell array. The control circuit executes a pre-erase stress application operation in which, when an erase operation on one of the memory cells is executed, prior to the erase operation, a first voltage belonging in a certain voltage range is applied to the control gate while a second voltage having a value smaller than a value of the first voltage is applied to the channel region, whereby a stress is applied to the memory cell due to a potential difference between the first voltage and the second voltage.