Invention Grant
- Patent Title: Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
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Application No.: US13047602Application Date: 2011-03-14
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Publication No.: US08553470B2Publication Date: 2013-10-08
- Inventor: Terry R. Lee , Joseph M. Jeddeloh
- Applicant: Terry R. Lee , Joseph M. Jeddeloh
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C7/10
- IPC: G11C7/10

Abstract:
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.
Public/Granted literature
- US08238171B2 Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules Public/Granted day:2012-08-07
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