Invention Grant
US08554824B2 Efficient technique for optimal re-use of hardware in the implementation of instructions used in viterbi, turbo and LPDC decoders
有权
在维特比,涡轮增压和LPDC解码器中使用的指令的实现中,可以最佳地重用硬件的技术
- Patent Title: Efficient technique for optimal re-use of hardware in the implementation of instructions used in viterbi, turbo and LPDC decoders
- Patent Title (中): 在维特比,涡轮增压和LPDC解码器中使用的指令的实现中,可以最佳地重用硬件的技术
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Application No.: US12874699Application Date: 2010-09-02
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Publication No.: US08554824B2Publication Date: 2013-10-08
- Inventor: Shriram D. Moharil , Timothy D. Anderson
- Applicant: Shriram D. Moharil , Timothy D. Anderson
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G06F7/50
- IPC: G06F7/50

Abstract:
Low density parity check (LDPC) decoding can be mapped to a class of DSP instructions called MINST. The MINST class of instructions significantly enhance the efficiency of LDPC decoding by merging several of the functions required by LDPC decoders into a single MINST instruction. This invention is an efficient implementation of the MINST class of instructions using a configurable three input arithmetic logic unit. The carry output results of the three input arithmetic logic unit enable permit boundary decisions in a range determination required by the MINST instruction. The preferred embodiment employs 2's complement arithmetic and carry-save adder logic. This invention allows reuse of hardware required to implement MAX* functions in LDPC functions.
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