An interface for a dynamic random access memory (DRAM) includes an interface element coupled to a DRAM chip using a first attachment structure, a first portion of the first attachment structure being used to form a wide bandwidth, low speed, parallel interface, a second portion of the first attachment structure, a routing element and a through silicon via (TSV) associated with the DRAM chip being used to form a narrow bandwidth, high speed, serial interface, the interface element configured to convert parallel information to serial information and configured to convert serial information to parallel information.