Invention Grant
US08555215B2 Methods for decomposing circuit design layouts and for fabricating semiconductor devices using decomposed patterns 有权
分解电路设计布局和使用分解模式制造半导体器件的方法

Methods for decomposing circuit design layouts and for fabricating semiconductor devices using decomposed patterns
Abstract:
Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.
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