Invention Grant
- Patent Title: Methods for decomposing circuit design layouts and for fabricating semiconductor devices using decomposed patterns
- Patent Title (中): 分解电路设计布局和使用分解模式制造半导体器件的方法
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Application No.: US13400445Application Date: 2012-02-20
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Publication No.: US08555215B2Publication Date: 2013-10-08
- Inventor: Yi Zou , Swamy Maddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
- Applicant: Yi Zou , Swamy Maddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.
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