Invention Grant
- Patent Title: Circuit simulation method and semiconductor integrated circuit
- Patent Title (中): 电路仿真方法和半导体集成电路
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Application No.: US13471061Application Date: 2012-05-14
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Publication No.: US08555224B2Publication Date: 2013-10-08
- Inventor: Tomoyuki Ishizu , Kyouji Yamashita , Gaku Suzuki
- Applicant: Tomoyuki Ishizu , Kyouji Yamashita , Gaku Suzuki
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2010-277012 20101213
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
The present disclosure provides a method of performing circuit simulation of electrical characteristics of a transistor formed on a semiconductor substrate using calculators, each of which includes a memory. A first calculator receives mask layout data and distance-dependent data indicating a distance from the target transistor. Then, a second calculator calculates an area ratio of a layout pattern of a predetermined mask from the received mask layout data, and calculates a parameter α based on the area ratio and the distance-dependent data. Then, the second calculator B calculates a change ΔP in the electrical characteristics of the transistor based on the parameter α. This configuration provides highly accurate circuit simulation of the electrical characteristics of the transistor, which depend on variations in temperature distribution of the semiconductor substrate during heat treatment due to the mask layout pattern around the transistor.
Public/Granted literature
- US20120227016A1 CIRCUIT SIMULATION METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2012-09-06
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