Invention Grant
US08558285B2 Method using low temperature wafer bonding to fabricate transistors with heterojunctions of Si(Ge) to III-N materials
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使用低温晶片接合制造具有Si（Ge）至III-N材料的异质结的晶体管的方法
- Patent Title: Method using low temperature wafer bonding to fabricate transistors with heterojunctions of Si(Ge) to III-N materials
- Patent Title (中): 使用低温晶片接合制造具有Si（Ge）至III-N材料的异质结的晶体管的方法
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Application No.: US13069725Application Date: 2011-03-23
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Publication No.: US08558285B2Publication Date: 2013-10-15
- Inventor: Umesh K. Mishra , Lee S. McCarthy
- Applicant: Umesh K. Mishra , Lee S. McCarthy
- Applicant Address: US CA Oakland
- Assignee: The Regents of the University of California
- Current Assignee: The Regents of the University of California
- Current Assignee Address: US CA Oakland
- Agency: Gates & Cooper LLP
- Main IPC: H01L29/72
- IPC: H01L29/72
Abstract:
A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.
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