Invention Grant
- Patent Title: Margin test methods and circuits
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Application No.: US12606159Application Date: 2009-10-26
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Publication No.: US08559493B2Publication Date: 2013-10-15
- Inventor: Andrew Ho , Vladimir Stojanovic , Bruno W. Garlepp , Fred F. Chen
- Applicant: Andrew Ho , Vladimir Stojanovic , Bruno W. Garlepp , Fred F. Chen
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Silicon Edge Law Group LLP
- Agent Arthur J. Behiel
- Main IPC: H04B3/46
- IPC: H04B3/46 ; H03K9/00

Abstract:
Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.
Public/Granted literature
- US20100074314A1 Margin Test Methods And Circuits Public/Granted day:2010-03-25
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