Invention Grant
US08560813B2 Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision
有权
具有快速和慢速路径的多线程处理器管线发出不同复杂度的不同指令集和避免冲突的指令
- Patent Title: Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision
- Patent Title (中): 具有快速和慢速路径的多线程处理器管线发出不同复杂度的不同指令集和避免冲突的指令
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Application No.: US12383118Application Date: 2009-03-19
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Publication No.: US08560813B2Publication Date: 2013-10-15
- Inventor: Andrew David Webber
- Applicant: Andrew David Webber
- Applicant Address: GB Kings Langley, Hertfordshire
- Assignee: Imagination Technologies Limited
- Current Assignee: Imagination Technologies Limited
- Current Assignee Address: GB Kings Langley, Hertfordshire
- Agency: ArtesynIP, Inc.
- Agent Michael S. Garrabrants
- Main IPC: G06F9/38
- IPC: G06F9/38

Abstract:
A method and apparatus are provided for executing instructions from a plurality of instruction threads on a multi-threaded processor. The instruction threads may each include instructions of different complexity. A plurality of pipelines for executing instructions are provided and an instruction scheduler determines on each clock cycle the pipelines upon which instructions will be executed. Some of the pipelines are configured to appear to the instruction threads as single pipelines but in fact include two pipeline paths, one for executed instructions of lower complexity and the other. The instruction scheduler determines on which of the two pipeline paths an instruction should execute.
Public/Granted literature
- US20090249037A1 Pipeline processors Public/Granted day:2009-10-01
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