Invention Grant
US08561005B2 Programmatic auto-convergent method for physical design floorplan aware re-targetable tool suite generation (compiler-in-the-loop) for simultaneous instruction level (software) power optimization and architecture level performance optimization for ASIP design
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用于ASIP设计的同步指令级（软件）功耗优化和架构级性能优化的物理设计平面图计划感知可重定向工具套件生成（编译器在循环）的程序化自动收敛方法
- Patent Title: Programmatic auto-convergent method for physical design floorplan aware re-targetable tool suite generation (compiler-in-the-loop) for simultaneous instruction level (software) power optimization and architecture level performance optimization for ASIP design
- Patent Title (中): 用于ASIP设计的同步指令级（软件）功耗优化和架构级性能优化的物理设计平面图计划感知可重定向工具套件生成（编译器在循环）的程序化自动收敛方法
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Application No.: US13452891Application Date: 2012-04-22
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Publication No.: US08561005B2Publication Date: 2013-10-15
- Inventor: Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
- Applicant: Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
- Applicant Address: US CA Sunnyvale
- Assignee: Algotochip Corp.
- Current Assignee: Algotochip Corp.
- Current Assignee Address: US CA Sunnyvale
- Agency: Tran & Associates
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50
Abstract:
Systems and methods are disclosed to automatically synthesize a custom integrated circuit by automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
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