A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the “1” to the carry in of the two's complement arithmetic unit. To execute a subtraction instruction using two's complement arithmetic, the subtraction as disclosed herein is performed in accordance with the identity “A−B=not (not (A)+B),” where A is a first operand and B is a second operand that is to be subtracted from A. Accordingly, the addition of the “1” term into the carry in is eliminated, and reduces a level of complexity that would otherwise slow down and/or limit the speed at which a subtraction instruction can be performed.