Invention Grant
US08572300B2 Physical coding sublayer (PCS) architecture for synchronizing data between different reference clocks
有权
用于在不同参考时钟之间同步数据的物理编码子层(PCS)架构
- Patent Title: Physical coding sublayer (PCS) architecture for synchronizing data between different reference clocks
- Patent Title (中): 用于在不同参考时钟之间同步数据的物理编码子层(PCS)架构
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Application No.: US13281505Application Date: 2011-10-26
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Publication No.: US08572300B2Publication Date: 2013-10-29
- Inventor: Shih-Chi Wu , Meng-Chin Tsai , Liang-Hung Chen , Jung-Chi Huang
- Applicant: Shih-Chi Wu , Meng-Chin Tsai , Liang-Hung Chen , Jung-Chi Huang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: G06F3/00
- IPC: G06F3/00

Abstract:
A physical coding sublayer includes a first channel configured to receive a first encoded data stream from a physical media attachment layer and to provide a first decoded data stream to a media access layer. The first channel includes a first circuit configured to detect synchronization headers in the first encoded data stream received from the physical media attachment layer, a decoding circuit configured to decode the encoded data stream and to adjust a width of the received data from a first width to a second width based on a signal identifying the synchronization headers received from the first circuit, and a first single configured to compensate for clock differences between the physical media attachment layer and the media access layer to which the first buffer provides the first decoded data stream.
Public/Granted literature
- US20130111083A1 PCS ARCHITECTURE Public/Granted day:2013-05-02
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