Invention Grant
- Patent Title: Integrating formation of a replacement gate transistor and a non-volatile memory cell using an interlayer dielectric
- Patent Title (中): 使用层间电介质来整合替换栅晶体管和非易失性存储单元的形成
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Application No.: US13491760Application Date: 2012-06-08
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Publication No.: US08574987B1Publication Date: 2013-11-05
- Inventor: Mehul D. Shroff , Mark D. Hall
- Applicant: Mehul D. Shroff , Mark D. Hall
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent James L. Clingan, Jr.; Joanna G. Chiu
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A first dielectric layer is formed over a semiconductor layer in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer in the NVM and logic regions. The charge storage layer is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed over the semiconductor layer in the NVM and logic regions which surrounds the charge storage structure and the dummy gate. The dummy gate is replaced with a logic gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. A third dielectric layer is formed over the charge storage structure, and a control gate layer is formed over the third dielectric layer.
Information query
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