Invention Grant
US08574997B2 Method of using a catalytic layer to enhance formation of a capacitor stack
有权
使用催化剂层以增强电容器叠层形成的方法
- Patent Title: Method of using a catalytic layer to enhance formation of a capacitor stack
- Patent Title (中): 使用催化剂层以增强电容器叠层形成的方法
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Application No.: US13153691Application Date: 2011-06-06
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Publication No.: US08574997B2Publication Date: 2013-11-05
- Inventor: Hanhong Chen , Sandra Malhotra , Hiroyuki Ode , Xiangxin Rui
- Applicant: Hanhong Chen , Sandra Malhotra , Hiroyuki Ode , Xiangxin Rui
- Applicant Address: US CA San Jose JP Tokyo
- Assignee: Intermolecular, Inc.,Elpida Memory, Inc.
- Current Assignee: Intermolecular, Inc.,Elpida Memory, Inc.
- Current Assignee Address: US CA San Jose JP Tokyo
- Main IPC: H01L21/20
- IPC: H01L21/20

Abstract:
A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2−x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.
Public/Granted literature
- US20120309162A1 METHOD FOR ALD DEPOSITION RATE ENHANCEMENT Public/Granted day:2012-12-06
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