Invention Grant
US08575655B2 Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering
有权
具有高K金属栅极集成和SiGe沟道工程的PMOS器件的方法和结构
- Patent Title: Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering
- Patent Title (中): 具有高K金属栅极集成和SiGe沟道工程的PMOS器件的方法和结构
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Application No.: US13431328Application Date: 2012-03-27
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Publication No.: US08575655B2Publication Date: 2013-11-05
- Inventor: Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
- Applicant: Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Joseph P. Abate, Esq.
- Main IPC: H01L29/66
- IPC: H01L29/66
Abstract:
Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.
Public/Granted literature
- US20120181631A1 METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING Public/Granted day:2012-07-19
Information query
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