Invention Grant
- Patent Title: Charge breakdown avoidance for MIM elements in SOI base technology and method
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Application No.: US13116416Application Date: 2011-05-26
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Publication No.: US08575668B2Publication Date: 2013-11-05
- Inventor: William F. Clark, Jr. , Stephen E. Luce
- Applicant: William F. Clark, Jr. , Stephen E. Luce
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran & Cole, P.C.
- Agent Anthony Canale
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/94
Abstract:
A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate.
Public/Granted literature
- US20110221030A1 CHARGE BREAKDOWN AVOIDANCE FOR MIM ELEMENTS IN SOI BASE TECHNOLOGY AND METHOD Public/Granted day:2011-09-15
Information query
IPC分类:
