Invention Grant
- Patent Title: Semiconductor device layout reducing imbalance characteristics of paired transistors
- Patent Title (中): 半导体器件布局减少成对晶体管的不平衡特性
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Application No.: US13034160Application Date: 2011-02-24
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Publication No.: US08575703B2Publication Date: 2013-11-05
- Inventor: Tomoyuki Ishizu
- Applicant: Tomoyuki Ishizu
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2008-294818 20081118
- Main IPC: H01L21/70
- IPC: H01L21/70

Abstract:
In a semiconductor device having paired transistors, an imbalance in characteristics of the paired transistors is reduced or prevented while an increase in circuit area is reduced or prevented. First and second transistors have first and second regions having the same active region pattern, and third and fourth transistors have third and fourth regions having the same active region pattern. The active regions of the third and fourth transistors have a longer length in the channel length direction than that of the active regions of the first and second transistors. The third and fourth regions have a narrower width in the channel length direction than that of the first and second regions.
Public/Granted literature
- US20110204448A1 SEMICONDUCTOR DEVICE Public/Granted day:2011-08-25
Information query
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