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US08575703B2 Semiconductor device layout reducing imbalance characteristics of paired transistors 有权
半导体器件布局减少成对晶体管的不平衡特性

Semiconductor device layout reducing imbalance characteristics of paired transistors
Abstract:
In a semiconductor device having paired transistors, an imbalance in characteristics of the paired transistors is reduced or prevented while an increase in circuit area is reduced or prevented. First and second transistors have first and second regions having the same active region pattern, and third and fourth transistors have third and fourth regions having the same active region pattern. The active regions of the third and fourth transistors have a longer length in the channel length direction than that of the active regions of the first and second transistors. The third and fourth regions have a narrower width in the channel length direction than that of the first and second regions.
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