Invention Grant
- Patent Title: Cascaded class D amplifier with improved linearity
- Patent Title (中): 级联D类放大器具有提高的线性度
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Application No.: US13410733Application Date: 2012-03-02
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Publication No.: US08576003B2Publication Date: 2013-11-05
- Inventor: Martin Kinyua , Ruopeng Wang
- Applicant: Martin Kinyua , Ruopeng Wang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H03F3/38
- IPC: H03F3/38 ; H03K9/08

Abstract:
An amplifier includes first and second stages. The first stage includes an input node for receiving an analog input signal, an analog digital converter for converting the analog input signal to a digital input signal, and a first switching circuit for outputting a first analog intermediate output signal in response to receiving a digital pulse width modulated signal that is based on the digital input signal. The second stage is configured to receive a pulse width modulation quantization error of the first stage, scale the pulse width modulation quantization error of the first stage by a gain factor to produce a scaled pulse width modulation quantization error of the first stage, and output a second analog intermediate output signal based on the scaled pulse width modulation quantization error of the first stage. A summation circuit combines the first and second analog intermediate output signals to generate an amplified output signal.
Public/Granted literature
- US20130229230A1 CASCADED CLASS D AMPLIFIER WITH IMPROVED LINEARITY Public/Granted day:2013-09-05
Information query
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