Respective lines forming a positive-polarity signal pixel circuit part, such as a Vdd line 102, a Cs1-connecting line 104 and a line 106 for a data line Di+, and respective lines forming a negative-polarity signal pixel circuit part, such as a Vdd line 103, a Cs2-connecting line 105 and a line 107 for a data line Di−, are arranged symmetrically to each other with respect to a pixel center line II-II′, respectively. Since the Vdd line 102 and the Vdd line 103 are positioned at right and left ends in one pixel, they serve as guard patterns to restrict crosstalk originating in either a Cs1-connecting line or a Cs2-connecting line of adjacent left and right pixels. The line 106 for the data line Di+ and the line 107 for the data line Di− are arranged in the vicinity of a central portion of the pixel.