A thin film transistor array panel which includes a substrate; a first gate line disposed on the substrate; a second gate line disposed adjacent to the first gate line; a gate insulating layer disposed on the first gate line and the second gate line; a semiconductor pattern disposed on the gate insulating layer and overlapping with the first gate line; a data line crossing the first gate line and the second gate line; a thin film transistor connected to the second gate line and the data line; and a floating electrode disposed on the semiconductor pattern, wherein the floating electrode is disposed at a same layer as the data line.