Invention Grant
US08576612B2 Low leakage high performance static random access memory cell using dual-technology transistors
有权
低泄漏高性能静态随机存取存储单元采用双工晶体管
- Patent Title: Low leakage high performance static random access memory cell using dual-technology transistors
- Patent Title (中): 低泄漏高性能静态随机存取存储单元采用双工晶体管
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Application No.: US13102961Application Date: 2011-05-06
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Publication No.: US08576612B2Publication Date: 2013-11-05
- Inventor: Manish Garg , Chiaming Chai , Michael ThaiThanh Phan
- Applicant: Manish Garg , Chiaming Chai , Michael ThaiThanh Phan
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Peter Michael Kamarchik; Nicholas J. Pauley; Joseph Agusta
- Main IPC: G11C11/00
- IPC: G11C11/00
Abstract:
A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.
Public/Granted literature
- US20110211386A1 Low Leakage High Performance Static Random Access Memory Cell Using Dual-Technology Transistors Public/Granted day:2011-09-01
Information query
