Invention Grant
- Patent Title: Memory array with inverted data-lines pairs
- Patent Title (中): 具有反相数据线对的存储器阵列
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Application No.: US13178278Application Date: 2011-07-07
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Publication No.: US08576627B2Publication Date: 2013-11-05
- Inventor: Satoru Tamada
- Applicant: Satoru Tamada
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: G11C16/04
- IPC: G11C16/04
Abstract:
At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells.
Public/Granted literature
- US20110267882A1 MEMORY ARRAY WITH INVERTED DATA-LINES PAIRS Public/Granted day:2011-11-03
Information query
