Invention Grant
- Patent Title: Method and apparatus of pattern inspection and semiconductor inspection system using the same
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Application No.: US13344409Application Date: 2012-01-05
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Publication No.: US08577124B2Publication Date: 2013-11-05
- Inventor: Yasutaka Toyoda , Akiyuki Sugiyama , Ryoichi Matsuoka , Takumichi Sutani , Hidemitsu Naya
- Applicant: Yasutaka Toyoda , Akiyuki Sugiyama , Ryoichi Matsuoka , Takumichi Sutani , Hidemitsu Naya
- Applicant Address: JP Tokyo
- Assignee: Hitachi High-Technologies Corporation
- Current Assignee: Hitachi High-Technologies Corporation
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2005-177121 20050617
- Main IPC: G06K9/00
- IPC: G06K9/00 ; G21K7/00 ; G06F17/50

Abstract:
A pattern inspection apparatus can be provided, for example, in a scanning electron microscope system. When patterns of a plurality of layers are included in a SEM image, the apparatus separates the patterns according to each layer by using design data of the plurality of layers corresponding to the patterns. Consequently, the apparatus can realize inspection with use of only the pattern of a target layer to be inspected, pattern inspection differently for different layers, or detection of a positional offset between the layers.
Public/Granted literature
- US20120099781A1 METHOD AND APPARATUS OF PATTERN INSPECTION AND SEMICONDUCTOR INSPECTION SYSTEM USING THE SAME Public/Granted day:2012-04-26
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