There is provided a signal receiving apparatus including first to pth stage computers configured to apply, in a step-by-step manner, butterfly operations to 2N input values; and 2N registers configured to store values obtained by a p−1th stage computer wherein the pth stage computer includes (a) 2L butterfly operation circuits configured to transmit, from corresponding 2M output ports, values obtained by the butterfly operations based on values provided to 2M input ports and (b) 2L selecting circuits arranged corresponding to the butterfly operation circuits, each selecting circuit providing a value of a register corresponding to different one of 2L BFInOrder_i(j,t) (wherein, BFInOrder_i(j,t) denotes values obtained by converting BFOutOrder_i(j,t)=t+j*2(N−M)+i*2N−(M+L) or (2(N−(M+L))−1−t)+j*2(N−M)+i*2(N−(M+L)) expressed by base H to base 2M of (log2M 2N)−1 words, word-reversing the values converted to base 2M, and converting the word-reversed values to the base H).