Invention Grant
- Patent Title: Apparatus for calculating and prefetching a branch target address
- Patent Title (中): 用于计算和预取分支目标地址的装置
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Application No.: US13423145Application Date: 2012-03-16
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Publication No.: US08578135B2Publication Date: 2013-11-05
- Inventor: Teppei Hirotsu , Yuuichi Abe , Takeshi Kataoka , Yasuhiro Nakatsuka
- Applicant: Teppei Hirotsu , Yuuichi Abe , Takeshi Kataoka , Yasuhiro Nakatsuka
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: JP2004-021207 20040129
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/40 ; G06F15/00

Abstract:
A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.
Public/Granted literature
- US20120173850A1 INFORMATION PROCESSING APPARATUS Public/Granted day:2012-07-05
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