Invention Grant
- Patent Title: ASIP architecture for executing at least two decoding methods
- Patent Title (中): 用于执行至少两个解码方法的ASIP架构
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Application No.: US12752944Application Date: 2010-04-01
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Publication No.: US08578238B2Publication Date: 2013-11-05
- Inventor: Robert Priewasser , Bruno Bougard , Frederik Naessens
- Applicant: Robert Priewasser , Bruno Bougard , Frederik Naessens
- Applicant Address: BE Leuven KR Suwon-si, Gyeonggi-do
- Assignee: IMEC,Samsung Electronics Co., Ltd.
- Current Assignee: IMEC,Samsung Electronics Co., Ltd.
- Current Assignee Address: BE Leuven KR Suwon-si, Gyeonggi-do
- Agency: Knobbe Martens Olson & Bear LLP
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
A system for execution of a decoding method is disclosed. The system is capable of executing at least two data decoding methods which are different in underlying coding principle, wherein at least one of the data decoding methods requires data shuffling operations on the data. In one aspect, the system includes at least one application specific processor having an instruction set having arithmetic operators excluding multiplication, division and power. The processor is selected for execution of approximations of each of the at least two data decoding methods. The system also includes at least a first memory unit, e.g. background memory, for storing data. The system also includes a transfer unit for transferring data from the first memory unit towards the at least one programmable processor. The transfer unit includes a data shuffler. The system may also include a controller for controlling the data shuffler independent from the processor.
Public/Granted literature
- US20100268918A1 ASIP ARCHITECTURE FOR EXECUTING AT LEAST TWO DECODING METHODS Public/Granted day:2010-10-21
Information query
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