Invention Grant
- Patent Title: Method and apparatus for performing asynchronous and synchronous reset removal during synthesis
- Patent Title (中): 在合成期间执行异步和同步复位去除的方法和装置
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Application No.: US12800227Application Date: 2010-05-11
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Publication No.: US08578306B2Publication Date: 2013-11-05
- Inventor: Valavan Manohararajah
- Applicant: Valavan Manohararajah
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agent L. Cho
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method for designing a system on a target device is disclosed. A system is synthesized by converting a high level description of the system into gates, registers, and reset circuitry. An analysis is performed to identify and remove redundant reset circuitry. The system is optimized after the redundant reset circuitry has been removed. Other embodiments are disclosed.
Public/Granted literature
- US20110283250A1 Method and apparatus for performing asynchronous and synchronous reset removal during synthesis Public/Granted day:2011-11-17
Information query
