A display device includes a display panel, a gate driver circuit, a source driver circuit, a timing control circuit, current detection circuits, and a programmable voltage generator. The display panel includes display pixel cells and redundancy pixel cells. The gate driver circuit is connected to the display panel via scan lines. The source driver circuit is connected to the display panel via data lines. The timing control circuit is connected to the gate driver circuit, the source driver circuit and the display panel via at least one redundancy scan line. Each of the current detection circuits is adopted for detecting one of the redundancy pixel cells and a working current of one of the display pixel cells to be compensated respectively when the display device enters the compensation mode. The programmable voltage generator is connected to the timing control circuit and the source driver circuit.