A semiconductor storage device includes: a cell array including a plurality of first wirings, a plurality of second wirings intersecting the first wirings, and memory cells positioned at intersecting portions between the first wirings and the second wirings, each of the memory cells having a series circuit of a non-ohmic element and a variable resistance element; a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit from a low resistance state to a high resistance state, to the memory cells through the first wirings and the second wirings; and a bias voltage application circuit configured to apply a bias voltage, which suppresses a potential variation caused by the transition of the variable resistance element from the low resistance state to the high resistance state, to one end of the variable resistance element.