Invention Grant
- Patent Title: Three dimensional stacked nonvolatile semiconductor memory
- Patent Title (中): 三维堆叠非易失性半导体存储器
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Application No.: US13738660Application Date: 2013-01-10
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Publication No.: US08582361B2Publication Date: 2013-11-12
- Inventor: Hiroshi Maejima
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2008-112660 20080423
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential higher than the read potential is applied to the word line in the first block in a state that a ground potential is applied to a channel of a memory cell existing nearer to the bit line side than a memory cell in the second cell unit to which the read potential is applied, after which all the memory cells in the second cell unit are cut off from the bit line, the bit line is set to a precharge potential, and read is performed to the a memory cell to be read in the first cell unit.
Public/Granted literature
- US20130121077A1 THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY Public/Granted day:2013-05-16
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