Invention Grant
US08584064B2 Verification support apparatus and verification support method to verify target circuit based on hardware description information 有权
基于硬件描述信息验证支持设备和验证支持方法来验证目标电路

  • Patent Title: Verification support apparatus and verification support method to verify target circuit based on hardware description information
  • Patent Title (中): 基于硬件描述信息验证支持设备和验证支持方法来验证目标电路
  • Application No.: US12949094
    Application Date: 2010-11-18
  • Publication No.: US08584064B2
    Publication Date: 2013-11-12
  • Inventor: Akio Matsuda
  • Applicant: Akio Matsuda
  • Applicant Address: JP Kawasaki
  • Assignee: Fujitsu Limited
  • Current Assignee: Fujitsu Limited
  • Current Assignee Address: JP Kawasaki
  • Agency: Fujitsu Patent Center
  • Priority: JP2009-264234 20091119
  • Main IPC: G06F9/455
  • IPC: G06F9/455 G06F17/50 G06F11/22 G06F9/44
Verification support apparatus and verification support method to verify target circuit based on hardware description information
Abstract:
A non-transitory, recording medium stores therein a program that causes a computer to execute extracting from hardware description of a circuit, a conditional branch statement representing a conditional branch process; determining whether the extracted conditional branch statement includes at least three condition expressions, where a given combination thereof has exclusive satisfying conditions; extracting from the conditional branch statement determined at the determining, a combination of condition expressions for which satisfying conditions are exclusive; extracting each condition expression from the extracted combination and creating, for each extracted condition expression and according to an order of appearance in the hardware description, a conditional branch statement in which the extracted condition expression has a hierarchical relationship with a condition expression not included in the combination; generating an assertion for checking whether a specified condition is satisfied in each created conditional branch statement; and outputting, as assertion data of the circuit, the generated assertion.
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