Invention Grant
- Patent Title: Fabrication method for circuit substrate having post-fed die side power supply connections
- Patent Title (中): 具有后馈模头侧电源连接的电路基板的制造方法
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Application No.: US12874397Application Date: 2010-09-02
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Publication No.: US08586476B2Publication Date: 2013-11-19
- Inventor: Daniel Douriet , Francesco Preda , Brian L. Singletary , Lloyd A. Walls
- Applicant: Daniel Douriet , Francesco Preda , Brian L. Singletary , Lloyd A. Walls
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Mitch Harris, Atty at Law, LLC
- Agent Andrew M. Harris; Matthew W. Baca
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.
Public/Granted literature
- US20100330797A1 FABRICATION METHOD FOR CIRCUIT SUBSTRATE HAVING POST-FED DIE SIDE POWER SUPPLY CONNECTIONS Public/Granted day:2010-12-30
Information query
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