Invention Grant
US08589611B2 Asynchronous logic circuit, semiconductor circuit, and path calculation method in asynchronous logic circuit 失效
异步逻辑电路,半导体电路和异步逻辑电路中的路径计算方法

  • Patent Title: Asynchronous logic circuit, semiconductor circuit, and path calculation method in asynchronous logic circuit
  • Patent Title (中): 异步逻辑电路,半导体电路和异步逻辑电路中的路径计算方法
  • Application No.: US13379614
    Application Date: 2010-06-09
  • Publication No.: US08589611B2
    Publication Date: 2013-11-19
  • Inventor: Katsunori Tanaka
  • Applicant: Katsunori Tanaka
  • Applicant Address: JP Tokyo
  • Assignee: NEC Corporation
  • Current Assignee: NEC Corporation
  • Current Assignee Address: JP Tokyo
  • Priority: JP2009-151351 20090625; JP2009-271516 20091130
  • International Application: PCT/JP2010/059768 WO 20100609
  • International Announcement: WO2010/105654 WO 20101229
  • Main IPC: G06F12/00
  • IPC: G06F12/00
Asynchronous logic circuit, semiconductor circuit, and path calculation method in asynchronous logic circuit
Abstract:
An asynchronous branching module (102) outputs transfer data received in accordance with a handshake protocol to any of branch destinations. An asynchronous arbitration module (101) merges transfer paths of the transfer data. A congestion detection module (111) receives an arbitration result signal from the asynchronous arbitration module (101) and outputs congestion information indicating presence/absence of congestion to a merge source. A congestion avoiding path calculation module (112) receives the congestion information and exclusively performs a process of storing the congestion information into a congestion information storage memory, and a process of making the asynchronous branching module (102) preferentially select, as a transfer branch destination, a branch destination generating no congestion information indicative of the presence of congestion from branch destinations leading to a destination, on the basis of the congestion information and the destination information of the transfer data.
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