A memory controller includes a comparison circuitry configured to compare the barrier context value of each write request to be issued to the memory with the barrier context values of at least some pending read requests, the pending read requests being requests received at the memory controller but not yet issued to the memory and, in response to detecting at least one of the pending read requests with an earlier barrier context value identifying a barrier transaction that has a corresponding barrier transaction in the stream of requests on the write channel that is earlier in the stream of requests than the write request, stalling the write request until the at least one pending read request has been performed; and, in response to detecting no pending read requests with the earlier barrier context value, issuing the write request to the memory.