Invention Grant
- Patent Title: Total power optimization for a logic integrated circuit
- Patent Title (中): 逻辑集成电路的总功率优化
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Application No.: US13103461Application Date: 2011-05-09
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Publication No.: US08589853B2Publication Date: 2013-11-19
- Inventor: Benjamin Mbouombouo , Ramnath Venkatraman , Ruggero Castagnetti
- Applicant: Benjamin Mbouombouo , Ramnath Venkatraman , Ruggero Castagnetti
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50

Abstract:
A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.
Public/Granted literature
- US20120290994A1 TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT Public/Granted day:2012-11-15
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