Invention Grant
US08592241B2 Method for packaging an electronic device assembly having a capped device interconnect
有权
用于封装具有封盖器件互连件的电子器件组件的方法
- Patent Title: Method for packaging an electronic device assembly having a capped device interconnect
- Patent Title (中): 用于封装具有封盖器件互连件的电子器件组件的方法
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Application No.: US13246990Application Date: 2011-09-28
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Publication No.: US08592241B2Publication Date: 2013-11-26
- Inventor: Scott M. Hayes , Jason R. Wright
- Applicant: Scott M. Hayes , Jason R. Wright
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Jonathan N. Geld
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
A method for fabricating a thin package that encapsulates a capped MEMS device electrically coupled with one or more encapsulated semiconductor devices is provided. A wafer-level packaging methodology is used in which the capped MEMS device is electrically coupled to a package interconnect, which then allows for electrical coupling to the one or more encapsulated semiconductor devices, as well as external connections.
Public/Granted literature
- US20130078753A1 CAPPED DEVICE INTERCONNECT IN A SEMICONDUCTOR PACKAGE Public/Granted day:2013-03-28
Information query
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