Invention Grant
US08592277B2 Method of forming low resistance gate for power MOSFET applications
有权
形成用于功率MOSFET应用的低电阻栅极的方法
- Patent Title: Method of forming low resistance gate for power MOSFET applications
- Patent Title (中): 形成用于功率MOSFET应用的低电阻栅极的方法
-
Application No.: US12891147Application Date: 2010-09-27
-
Publication No.: US08592277B2Publication Date: 2013-11-26
- Inventor: Sreevatsa Sreekantham , Ihsiu Ho , Fred Session , James Kent Naylor
- Applicant: Sreevatsa Sreekantham , Ihsiu Ho , Fred Session , James Kent Naylor
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method for forming a trench gate field effect transistor includes forming, in a semiconductor region, a trench followed by forming a dielectric layer lining a sidewall and a bottom surface of the trench. The method also includes, forming a first polysilicon layer on the bottom surface of the trench. The method further includes, forming a conductive material layer on an exposed surface of the first polysilicon layer and forming a second polysilicon layer on an exposed surface of the conductive material layer. The method still further includes, performing rapid thermal processing to cause the first polysilicon layer, the second polysilicon layer and the conductive material layer to react.
Public/Granted literature
- US20110014763A1 Method of Forming Low Resistance Gate for Power MOSFET Applications Public/Granted day:2011-01-20
Information query
IPC分类: