Invention Grant
- Patent Title: Wiring structure, semiconductor device and manufacturing method thereof
- Patent Title (中): 接线结构，半导体器件及其制造方法
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Application No.: US13137622Application Date: 2011-08-30
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Publication No.: US08592283B2Publication Date: 2013-11-26
- Inventor: Fuminori Ito , Yoshihiro Hayashi , Tsuneo Takeuchi
- Applicant: Fuminori Ito , Yoshihiro Hayashi , Tsuneo Takeuchi
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: McGinn Intellectual Property Law Group, PLLC
- Priority: JP2005-270355 20050916; JP2006-198752 20060720
- Main IPC: H01L21/70
- IPC: H01L21/70
Abstract:
A semiconductor device manufacturing method for manufacturing a semiconductor device having a transistor mounted in a wiring of a plural-layer structure includes in manufacturing the semiconductor device that is formed on a semiconductor element and includes a barrier insulating film, a porous interlayer insulating film, a wiring, a via plug formed by embedding a metal wiring material in a wiring trench, and a via hole formed in the porous interlayer insulating film, irradiating an electron beam or an ultraviolet ray onto at least a portion of the porous interlayer insulating film before forming an opening in the barrier insulating film.
Public/Granted literature
- US20110318926A1 Wiring structure, semiconductor device and manufacturing method thereof Public/Granted day:2011-12-29
Information query
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