Invention Grant
US08592301B2 Template wafer fabrication process for small pitch flip-chip interconnect hybridization
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用于小间距倒装芯片互连杂交的模板晶片制造工艺
- Patent Title: Template wafer fabrication process for small pitch flip-chip interconnect hybridization
- Patent Title (中): 用于小间距倒装芯片互连杂交的模板晶片制造工艺
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Application No.: US13873501Application Date: 2013-04-30
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Publication No.: US08592301B2Publication Date: 2013-11-26
- Inventor: Justin K. Markunas , Eric F. Schulte
- Applicant: The United States of America, as Represented by the Secretary of the Army
- Applicant Address: US DC Washington
- Assignee: The United States of America as represented by the Secretary of the Army
- Current Assignee: The United States of America as represented by the Secretary of the Army
- Current Assignee Address: US DC Washington
- Agent Richard J. Kim
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
A template wafer fabrication process is disclosed for high density indium bumping of microchips by using an innovative template wafer upon which the bumps are initially fabricated. Once fabricated, these bumps are transferred to the microchip, after which can be hybridized to another microchip. Such a template wafer is reusable, and thus provides an economical way to fabricate indium bumps. Reusability also eliminates nonuniformities in bump shape and size in serial processing of separate microchips, which is not the case for other indium bump fabrication processes. Such a fabrication process provides a way to form relatively tall indium bumps and accomplishes this without the standard thick photoresist liftoff process. The described process can be suitable for bump pitches under 10 microns, and is only limited by the resolution of the photolithography equipment used.
Public/Granted literature
- US20130244417A1 Template Wafer Fabrication Process for Small Pitch Flip-Chip Interconnect Hybridization Public/Granted day:2013-09-19
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